1. Technical Field
The present disclosure relates to interconnection structures for flip-chip attachment of microelectronic device chips to packages.
2. Description of the Related Art
Three different interconnection technologies are employed to provide interconnection between a chip and a substrate (or chip carrier). These interconnection technologies are tape automated bonding (TAB), wirebonding, and area array. The area array is often call a flip-chip connection or C4 (controlled-collapse chip connection). The C4 technology uses solder bumps deposited on a solder-wettable layered structure known as a ball-limiting metallurgy (BLM) on the chip. Since the C4 technology uses an array of solder bumps that can be placed over the entire surface area of the chip, it can achieve a higher density of input/output interconnections and better power dissipation than can wirebonding or TAB, which confine the interconnections to the chip periphery.
A number of systems have been proposed and evaluated for fabrication of C4s using lead-free metallurgies. Lead-free solders, such as tin-based alloys, are now commonly used to avoid the harmful environmental effects of lead-based alloys. During the fabrication process of a BLM, a “plated through the mask” process is employed in which metallurgies, such as TiW/Cr/phased Cr/Cu/Ni/Pb-free alloy, are sequentially deposited
During hot storage, in which wafers are kept at 120-150° C. for over 1000 hours, voids form in the copper layer. These voids are apparently due to Ni—Cu/Sn intermetallics, which are in turn formed by Ni/Cu interdiffusion produced by long term thermal exposure. These voids lead to failure in the integrity of the BLM structure and are a reliability concern.